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Tag Archives:

A Hardware Accelerator for Computing an Exact Dot Product

John Koenig, David Biancolin, Jonathan Bachrach, Krste Asanovic
2017 IEEE International Symposium on Computer Arithmetic , Jul. 2017.
Tags: Accelerators, Chisel, RISC-V

The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor

Christopher Celio, David Patterson, Krste Asanovic
Technical Report No. UCB/EECS-2015-167, Jun. 2015.
Tags: BOOM, RISC-V, Technical Report

The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0

Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovic
Technical Report No. UCB/EECS-2014-54, May. 2014.
Tags: RISC-V, Technical Report

Instruction Sets Should Be Free: The Case For RISC-V

Krste Asanovic, David Patterson
Technical Report No. UCB/EECS-2014-146, Aug. 2014.
Tags: RISC-V, Technical Report

The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.0

Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovic
May. 2014.
Tags: RISC-V, Technical Report

Tags

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