Publications

• An Agile Approach to Building RISC-V Microprocessors
• A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI
• Hwacha Preliminary Evaluation Results, Version 3.8.1
• The Hwacha Microarchitecture Manual, Version 3.8.1
• The Hwacha Vector-Fetch Architecture Manual, Version 3.8.1
• A RISC-V Vector Processor with Tightly-Integrated Switched-Capacitor DC-DC Converters in 28nm FDSOI
• Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures
• The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0
• The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.0
• A Case for OS-Friendly Hardware Accelerators