As part of the celebration of the 50th anniversary of IEEE Computer magazine (see below), I’ve been asked to write a retrospective on “A VLSI RISC,” that was published in 1982.
It’s an interesting experience to (re)learn from a paper that you wrote 35 years ago. For example, which computer first had a register hardwired to zero? (The answer: the 1951 Ferranti-Manchester MADM, which was the first machine with index registers, also used a register to supply zero.)
By far the biggest surprise was how close is the original instruction set of the RISC-I to the base instruction set of RISC-V (RV32I). The figure below compares the two instruction sets.
While architects talk about the differences (register windows, condition codes, delayed branch), it’s amazing that there aren’t more after 30 years of innovation in computer architecture fueled by Moore’s Law and Dennard Scaling (1981 to 2011). Common features of RISC-I and RV32I:
- All instructions are 32-bit long
- 31 registers, with register 0 hardwired to zero, all 32 bits wide
- All operations are register-to-register, not register-to-memory
- They have the same arithmetic, logical, and shift operations
- They have the same load and store instructions
- Immediate option for all arithmetic, logical, and shift instructions
- Immediates always sign-extended
- One data addressing mode (register + immediate)
- PC-relative branching
- Signed and unsigned versions of load and store byte and halfword (called “short” in RISC-I)
- No multiply or divide instructions
Below is the complete ISA for both architectures, aligned by function.