ASPIRE graduate Student Yang You wins George Michael HPC Fellowship


Yang You’s research interests include scalable algorithms, parallel computing, distributed systems and machine learning. As computers increasingly use more time and energy to transfer data (i.e., communicate), the invention or identification of algorithms that reduce communication within systems is becoming increasingly essential. In well-received research papers, You has made several fundamental contributions that reduce the communications between levels of a memory hierarchy or between processors over a network.

In his most recent work, “Scaling Deep Learning on GPU and Knights Landing Clusters,” You’s goal is to scale up the speed of training neural networks so that networks which are relatively slow to train can be redesigned for high performance clusters. This approach has reduced the percentage of communication from 87% to 14% and resulted in a five-fold increase in speed.

The ACM/IEEE-CS George Michael Memorial HPC (GMM) Fellowship is endowed in memory of George Michael, one of the founding fathers of the SC Conference series. The fellowship honors exceptional PhD students throughout the world whose research focus is on high performance computing applications, networking, storage or large-scale data analytics using the most powerful computers that are currently available. The Fellowship includes a $5,000 honorarium and travel expenses to attend SC17 in Denver Colorado, November 12-17, 2017, where the GMM Fellowships will be formally presented.

Congratulations, Yang!

ACM Article

CPU architecture after Moore’s Law: What’s next? | Computerworld


As Moore’s Law loses relevance, specialization may have to replace raw speed in microprocessor design.

When considering the future of CPU architecture, some industry watchers predict excitement, and some predict boredom. But no one predicts a return to the old days, when speed doubled at least every other year.

The upbeat prognosticators include David Patterson, a professor at the University of California, Berkeley, who literally wrote the textbook (with John Hennessy) on computer architecture. “This will be a renaissance era for computer architecture — these will be exciting times,” he says.

Read Full Article Here

Paper co-authored by ASPIRE student Bichen Wu wins Embedded Vision Workshop of CVPR Best Paper Award


The Best Paper Award at the Embedded Vision Workshop of CVPR was presented to Bichen Wu, Forrest Iandola, Peter H. Jin, and Kurt Keutzer for “SqueezeDet: Unified, Small, Low Power Fully Convolutional Neural Networks for Real-Time Object Detection for Autonomous Driving”.  Congratulations to the team!

See the paper Here

Source code can be found Here



How close is RISC-V to RISC-I?

David Patterson

As part of the celebration of the 50th anniversary of IEEE Computer magazine (see below), I’ve been asked to write a retrospective on “A VLSI RISC,” that was published originally in 1982. (The retrospective appeared December 2017.)

It’s an interesting experience to (re)learn from a paper that you wrote 35 years ago. For example, which computer first had a register hardwired to zero? (The answer: the 1951 Ferranti-Manchester MADM, which was the first machine with index registers, also used a register to supply zero.)

By far the biggest surprise was how close is the original instruction set of the RISC-I to the base instruction set of RISC-V (RV32I). The figure below compares the two instruction sets.  In fact, RISC-I is may be the closest instruction set to RISC-V of any era; it is certainly much closer than the original Stanford MIPS and IBM 801 instruction sets.

While architects talk about the differences (register windows, condition codes, delayed branch),  it’s amazing that there aren’t more after 30 years of innovation in computer architecture fueled by Moore’s Law and Dennard Scaling (1981 to 2011). Common features of RISC-I and RV32I:

  • A 32-bit byte-addressable address space
  • All instructions are 32-bit long
  • 31 registers, with register 0 hardwired to zero, all 32 bits wide
  • All operations are register-to-register (none are register-to-memory)
  • The same arithmetic, logical, and shift operations
  • The same load word and store word instructions
  • Signed and unsigned versions of load and store byte and halfword (called “short” in RISC-I)
  • Immediate option for all arithmetic, logical, and shift instructions
  • Immediates are always sign-extended
  • One data addressing mode (register + immediate)
  • PC-relative branch addressing
  • No multiply or divide instructions
  • An instruction to load a wide immediate into the upper part of register so that a 32-bit constant takes only two instructions

Below is the complete ISA for both architectures, aligned by operation.

Equivalent RISC-V and RISC-I instructions. For RISC-I, “S2” can be either a 13-bit sign-extended immediate or a second source register.

From the Archives: Computer’s Legacy

Mihir Patil wins the Warren Dere Design Award!


Congratulations to ASPIRE’s Mihir Patil on winning the Warren Dere Design Award!  it was largely for his work on Project Hermione, an automatic camera-tracking system for recording class lectures based on the same technology Mihir worked with the SEJITS team on for doing object tracking in live video!

The Warren Dere Design Award award is presented to graduating seniors whose accomplishments in engineering design are judged to be most outstanding. Evidence might include accomplishments during a co-op or internship assignment or on a summer job, or achievements on a project for an upper division design course. This memorial award honors Professor Dere who also worked at IBM and was known to be outstanding in engineering systems design.

Well done, Mihir!

RISC-V Chosen as Best Technology of 2016 by the Linley Group


In a news release issued today, January 12th, 2017, The Linley Group today announced the winners of its annual Analysts’ Choice Awards which recognize the top semiconductor products of 2016 in seven categories: embedded processors, mobile processors, server processors, processor-IP cores, mobile chip, networking chip, and best technology.  The RISC-V Instruction Set Architecture was selected as the Best Technology of 2016.

For full article:

Scott Beamer receives 2016 SPEC Kaivalya Dixit Distinguished Dissertation Award


Dr. Scott Beamer’s dissertation titled “Undertanding and Improving Graph Algorithm Performance” has been selected to receive the 2016 Standard Performance Evaluation Corp (SPEC) Kaivalya Dixit Distinguished Dissertation Award.  The award recognizes outstanding doctoral dissertations in the field of computer benchmarking, performance evaluation, and experimental system analysis in general.  Papers are evaluated on scientific originality, scientific significance, practical relevance, impact, and quality of the presentation.

Among other comments, the members of the committee were impressed with Beamer’s deep understanding of open-source graphs, with the quality of the implementations, with the creation of a graph benchmark suite that is already been used, that is relevant for High Performance Computing, and that is likely to have further impact in the future. The committee also remarked on the clarity and simplicity of the ideas presented in the document.

The award will be presented at the International Conference on Performance Engineering (ICPE) in April.

Dave Patterson named winner of 2016 Richard A. Tapia Achievement Award


The Richard A. Tapia Achievement Award for Scientific Scholarship, Civic Science and Diversifying Computing is awarded yearly to an individual who demonstrates significant leadership, commitment and contributions to diversifying computing. Dr. David Patterson has been selected as the 2016 Richard A. Tapia Award recipient.

Dr. David Patterson grew up in Southern California body surfing and listening to the Beach Boys, who were a local band. He was the first of his family to graduate from college, earning three degrees from UCLA before joining UC Berkeley in 1976. Thus, his whole world since he was a teenager has been large public universities.
His most successful projects have likely been Reduced Instruction Set Computers (RISC), Redundant Arrays of Inexpensive Disks (RAID), and Network of Workstations (NOW). All three projects helped lead to multibillion-dollar industries. This research led to many papers and six books, with the best-known book being Computer Architecture: A Quantitative Approach, co-authored by John Hennessy, and the most-recent book being Engineering Software as a Service, co-authored by Armando Fox. His current research is open source computer architecture (RISC-V) and hardware for computer security.
In the past, he served as Director of the Parallel Computing Lab, Director of the Reliable And Distributed Systems Lab, Chair of UC Berkeley’s CS Division, Chair of the Computing Research Association (CRA), and President of the Association for Computing Machinery (ACM). He was General Chair of Tapia 2011, serves on its steering committee, and supports large UC Berkeley contingents that attend the conferences.
Dr. Patterson will be presented with the Richard A. Tapia Award at the Tapia Conference on Friday, September 16, 2016.