How close is RISC-V to RISC-I?

David Patterson

As part of the celebration of the 50th anniversary of IEEE Computer magazine (see below), I’ve been asked to write a retrospective on “A VLSI RISC,” that was published in 1982.

It’s an interesting experience to (re)learn from a paper that you wrote 35 years ago. For example, which computer first had a register hardwired to zero? (The answer: the 1951 Ferranti-Manchester MADM, which was the first machine with index registers, also used a register to supply zero.)

By far the biggest surprise was how close is the original instruction set of the RISC-I to the base instruction set of RISC-V (RV32I). The figure below compares the two instruction sets.

While architects talk about the differences (register windows, condition codes, delayed branch),  it’s amazing that there aren’t more after 30 years of innovation in computer architecture fueled by Moore’s Law and Dennard Scaling (1981 to 2011). Common features of RISC-I and RV32I:

  • All instructions are 32-bit long
  • 31 registers, with register 0 hardwired to zero, all 32 bits wide
  • All operations are register-to-register, not register-to-memory
  • They have the same arithmetic, logical, and shift operations
  • They have the same load and store instructions
  • Immediate option for all arithmetic, logical, and shift instructions
  • Immediates always sign-extended
  • One data addressing mode (register + immediate)
  • PC-relative branching
  • Signed and unsigned versions of load and store byte and halfword (called “short” in RISC-I)
  • No multiply or divide instructions

Below is the complete ISA for both architectures, aligned by function.

Equivalent RISC-V and RISC-I instructions

From the Archives: Computer’s Legacy

Mihir Patil wins the Warren Dere Design Award!


Congratulations to ASPIRE’s Mihir Patil on winning the Warren Dere Design Award!  it was largely for his work on Project Hermione, an automatic camera-tracking system for recording class lectures based on the same technology Mihir worked with the SEJITS team on for doing object tracking in live video!

The Warren Dere Design Award award is presented to graduating seniors whose accomplishments in engineering design are judged to be most outstanding. Evidence might include accomplishments during a co-op or internship assignment or on a summer job, or achievements on a project for an upper division design course. This memorial award honors Professor Dere who also worked at IBM and was known to be outstanding in engineering systems design.

Well done, Mihir!

RISC-V Chosen as Best Technology of 2016 by the Linley Group


In a news release issued today, January 12th, 2017, The Linley Group today announced the winners of its annual Analysts’ Choice Awards which recognize the top semiconductor products of 2016 in seven categories: embedded processors, mobile processors, server processors, processor-IP cores, mobile chip, networking chip, and best technology.  The RISC-V Instruction Set Architecture was selected as the Best Technology of 2016.

For full article:

Scott Beamer receives 2016 SPEC Kaivalya Dixit Distinguished Dissertation Award


Dr. Scott Beamer’s dissertation titled “Undertanding and Improving Graph Algorithm Performance” has been selected to receive the 2016 Standard Performance Evaluation Corp (SPEC) Kaivalya Dixit Distinguished Dissertation Award.  The award recognizes outstanding doctoral dissertations in the field of computer benchmarking, performance evaluation, and experimental system analysis in general.  Papers are evaluated on scientific originality, scientific significance, practical relevance, impact, and quality of the presentation.

Among other comments, the members of the committee were impressed with Beamer’s deep understanding of open-source graphs, with the quality of the implementations, with the creation of a graph benchmark suite that is already been used, that is relevant for High Performance Computing, and that is likely to have further impact in the future. The committee also remarked on the clarity and simplicity of the ideas presented in the document.

The award will be presented at the International Conference on Performance Engineering (ICPE) in April.

Dave Patterson named winner of 2016 Richard A. Tapia Achievement Award


The Richard A. Tapia Achievement Award for Scientific Scholarship, Civic Science and Diversifying Computing is awarded yearly to an individual who demonstrates significant leadership, commitment and contributions to diversifying computing. Dr. David Patterson has been selected as the 2016 Richard A. Tapia Award recipient.

Dr. David Patterson grew up in Southern California body surfing and listening to the Beach Boys, who were a local band. He was the first of his family to graduate from college, earning three degrees from UCLA before joining UC Berkeley in 1976. Thus, his whole world since he was a teenager has been large public universities.
His most successful projects have likely been Reduced Instruction Set Computers (RISC), Redundant Arrays of Inexpensive Disks (RAID), and Network of Workstations (NOW). All three projects helped lead to multibillion-dollar industries. This research led to many papers and six books, with the best-known book being Computer Architecture: A Quantitative Approach, co-authored by John Hennessy, and the most-recent book being Engineering Software as a Service, co-authored by Armando Fox. His current research is open source computer architecture (RISC-V) and hardware for computer security.
In the past, he served as Director of the Parallel Computing Lab, Director of the Reliable And Distributed Systems Lab, Chair of UC Berkeley’s CS Division, Chair of the Computing Research Association (CRA), and President of the Association for Computing Machinery (ACM). He was General Chair of Tapia 2011, serves on its steering committee, and supports large UC Berkeley contingents that attend the conferences.
Dr. Patterson will be presented with the Richard A. Tapia Award at the Tapia Conference on Friday, September 16, 2016.

A Berkeley Bash

David Patterson

Hoping to start a new tradition, I’m giving a Last Lecture on Friday May 6, 2016 at 4PM, which is shortly before I retire. (The premise of these is that if this were the last public lecture you would give, what would you say.) My title is “How to Be a Bad Professor” (abstract), and it is followed by a reception.

There will also be a one-day symposium on Saturday May 7 (agenda) with talks by colleagues and former students on the future of topics associated with my 40 years at UC Berkeley, such as the microprocessors, storage, cloud computing, data science, and machine learning.

Please sign up to the event of interest, and feel free to invite other interested parties. Both events will be held at the International House at UC Berkeley.

P.S. Those who sign up for the symposium before April 7 will get a commemorative book with perspectives by Stanford President John Hennessy, National Medal of Science Winner Richard Tapia, former UCSC Chancellor Karl Pister, and other luminaries.