Agile HW Design Center

Agile HW Design Center lab pledges to use and develop open-source software and hardware, and it is the intention of all Agile HW Design Center lab researchers that any software and hardware will be released under an open-source license, such as modified BSD or Apache 2.0

 

Intel Science and Technology Center for Agile HW Design:

The Intel Science and Technology Center (ISTC) for Agile HW Design is community of researchers co-located at UC Berkeley and Stanford University. This center funded by Intel labs’ University Research and Collaboration Dept focuses on new methodologies and processes for implementing Agile SW development methods in HW. The research funded under the center at UC Berkeley is described below while the research at Stanford is described at: https://aha.stanford.edu/

 

Description: New computing applications demand increased system capability, but as scaling slows, new approaches to both design and architecture of CPUs become increasingly important.

New architectures and rapid development methodologies are required to quickly generate efficient specialized chips for different markets. To provide for ultimate energy efficiency in a broad scope of applications ranging  from future mobile clients to warehouse ­scale computers (WSCs), The ISTC Agile Center at UC Berkeley proposes to develop new architectures that will optimally utilize a  computing substrate based on extremely scaled CMOS and some of the key emerging device, interconnect and memory technologies.

While workloads are constantly changing, the  underlying computational primitives are not. We have established the 13 Berkeley computational motifs as the key computational kernels across a wide range of current and emerging applications. By optimally implementing specialized engines for these motifs, including both computation and data movement, we can achieve optimal energy efficiency over a broad range of application domains and underlying technologies.

To reduce engineering effort and time ­to­ market for these specialized architectures, we propose new agile hardware design, simulation, and verification methodologies. We will build upon on our earlier work using the free and open RISC­V instruction set architecture and the open­ source Chisel hardware construction language supporting chip generators for agile hardware development. We will use two example architectures to drive our research work, the Berkeley FireBox WSC to represent future datacenter architectures, and an embedded programmable vision processor to represent future client devices.

 To demonstrate our agile approach, we will implement both these devices from a single generator code base, and iteratively improve these prototypes over the course of the project. All our research prototypes will be distributed as open ­source code under permissive licenses (Apache, MIT Open Source or BSD). 

Following the successful collaboration style of our earlier projects, the entire group will meet regularly to exchange ideas,
and will use the two prototype systems to continually integrate all the research from across the project.

Increasingly, our opensource code base is being used around the world both in academia and industry, and we will continue to use this approach to distribute our ideas to the global community.

 

Personnel:

Academic PI: Krste  Asanovic  is  a  Professor of  Electrical  Engineering and  Computer  Sciences at the  University of California at Berkeley.  He is also Director of the ASPIRE Lab and leads the RISC­V project at Berkeley. His primary research areas are computer architecture and VLSI design, and his various research projects have successfully fabricated several novel microprocessors. His recent relevant work is in the design of many core architectures, including data­parallel accelerators. Asanovic will also direct the architecture work within the ISTC. 

Academic Co-PI: Borivoje Nikolić is a National Semiconductor Distinguished Professor of Engineering at the University of California at Berkeley. He is also a scientific Co­Director of the Berkeley Wireless Research Center (BWRC) 

and presently co­leads the ASPIRE project.  His areas of expertise include digital and analog integrated circuit design and signal processing techniques in communications and data storage. Nikolic will lead the memory interface work within the ISTC and the chip implementation efforts.

Sanjit A. Seshia: He is an Associate Professor of Electrical Engineering and Computer Sciences at the University of California at Berkeley. His areas of expertise center on formal methods and computational logic applied  to  electronic  design  automation,  computer  security,  and  cyber­physical  systems. His core contributions include pioneering work in satisfiability modulo theories (SMT) solving, algorithmic program synthesis, model checking, and specification mining. Professor Seshia will lead the verification and security efforts within the ISTC.

Jonathan Bachrach: He is an Adjunct Assistant Professor at University of California at Berkeley. He leads the Chisel development effort and is involved in the ASPIRE and CRAFT DARPA projects.  His research is focussed on high­level software­defined hardware design methodologies. Bachrach will lead the work on Chisel in the ISTC.

Jonathan Ragan-­Kelley: He is an Assistant Professor of Electrical Engineering and Computer Sciences at the University  of  California  at  Berkeley. His work focuses on systems for efficient visual computing, from architectures,  through  languages,  compilers,  and  programming  models,  to  new  algorithms  for  image processing, computational photography, vision, and graphics. Most visibly, he created the Halide language for  high­performance  image  processing.  He has worked on GPU architecture and compilers at NVIDIA, AMD/ATI, and for two years at Intel as a member of the Advanced Rendering Technology group, and he continues to collaborate with the Intel Imaging and Camera Technologies Group on using Halide to target the programmable Silicon Hive image processors.  Ragan­Kelley will lead the definition of the image processing architecture and accompanying software stack.

Jeff Parkhurst: Dr. Parkhurst is the Center Director for the ISTC for Agile HW Design. He is responsible for assisting the PIs in managing the operational details in each center as well as driving direction setting of the research. The Center Director is the primary liaison between Intel and the universities on all research and operational matters including contracts, IP, funding, and technology/knowledge transfer. Prior to this assignment, Jeff was Program Director for the Intel Science and Technology Centers for Big Data, Cloud Computing and Visual Computing. Jeff received his BS from University of Nevada at Reno in 1983 and his MS from the University of California at Davis in 1988 and his PhD at Purdue University in 1994. He is the author of numerous papers and one patent. He has been at Intel Corporation since 1994.