Publications
- Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor
- A Hardware Accelerator for Computing an Exact Dot Product
- Grail Quest: A New Proposal for Hardware-assisted Garbage Collection
- Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL
- The Rocket Chip Generator
- Taurus: A Holistic Language Runtime System for Coordinating Distributed Managed-Language Applications
- Hwacha Preliminary Evaluation Results, Version 3.8.1
- The Hwacha Microarchitecture Manual, Version 3.8.1
- The Hwacha Vector-Fetch Architecture Manual, Version 3.8.1
- Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency
- GAIL: The Graph Algorithm Iron Law
- Locality Exists in Graph Processing: Workload Characterization on an Ivy Bridge Server
- The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor
- Trash Day: Coordinating Garbage Collection in Distributed Systems
- Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures
- The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0
- Instruction Sets Should Be Free: The Case For RISC-V
- Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors
- Joint Impact of Random Variations and RTN on Dynamic Writeability in 28nm Bulk and FDSOI SRAM
- The Case for the Holistic Language Runtime System
- The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.0
- PHANTOM: Practical Oblivious Computation in a Secure Processor
- A Hardware Evaluation of Cache Partitioning to Improve Utilization and Energy-Efficiency while Preserving Responsiveness
- A Case for OS-Friendly Hardware Accelerators
- Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search