This work-in-progress document outlines the fourth version of the Hwacha vector-fetch architecture. Inspired by traditional vector machines from the 1970s and 1980s such as the Cray-1 [13], and lessons learned from our previous vector-thread architectures such as Scale [9, 7] and Maven [5, 10, 12], the Hwacha architecture is designed to provide high performance at low power/energy for a wide range of applications while being a favorable compiler target. The main feature of the Hwacha architecture is exploiting a high degree of decoupling between vector data access and vector execution. Traditional vector architectures are known to provide some degree of decoupling, however, the Hwacha architecture pushes the limits of decoupling even further by exposing a vectorfetch assembly programming model that hoists out all vector instructions into a separate vector-fetch block. We first introduce the Hwacha vector-fetch assembly programming model, the abstract low-level software interface that gives programmers or compiler writers an idea of how code executes on the Hwacha machine, and also discuss key architectural features—in particular, how Hwacha contrasts with other data-parallel architectures, including packed SIMD, SIMT, and traditional vector. We then present the Hwacha instruction set architecture (ISA), and discuss some design decisions. In conjunction with this document, we have published two other documents that describe the microarchitecture and preliminary evaluation results. All documents are versioned 3.8.1 as they describe a snapshot of the current work that is in progress towards version 4.

EECS-2015-262