RISC-V is an open instruction set architecture (ISA) developed at Berkeley in the ParLab and ASPIRE projects.  RISC-V was originally designed to support computer architecture research and education, but  we now hope RISC-V will also become a standard open architecture for industry implementations. The base user-level ISA has now been frozen and a complete specification is available from the official RISC-V website at http:www.riscv.org, along with a comprehensive collection of tools.