Publications

• A Double-Tail Sense Amplifier for Low-Voltage SRAM in 28nm Technology
• Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor
• Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency
• Simpler, More Efficient Design
• A Differential 2R Crosspoint RRAM Array with Zero Standby Current
• Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors
• Joint Impact of Random Variations and RTN on Dynamic Writeability in 28nm Bulk and FDSOI SRAM