Memory power consumption dominates mobile
system energy budgets in scaled technologies. Fast nonvolatile
memories (NVMs) offer a tremendous opportunity to eliminate
memory leakage current during standby mode. Resistive random
access memory (RRAM) in a crosspoint structure is considered to
be one of the most promising emerging NVMs. However, the
absence of access transistors puts significant challenges on the
write/read operation. In this paper, we propose a differential 2R
crosspoint structure with array segmentation and
sense-before-write techniques. A 64KB RRAM is constructed and
simulated in a 28/32nm CMOS predictive technology model
(PTM) and a Verilog-A RRAM model. This design offers an
opportunity for using RRAM as a cache for increasing energy
efficiency in mobile computing.

A Differential 2R Crosspoint RRAM Array with Zero Standby Current