Design of the RISC-V Instruction Set Architecture

The hardware-software interface, embodied in the instruction set architecture (ISA), is arguably the most important interface in a computer system. Yet, in contrast to nearly all other interfaces in a modern computer system, all commercially popular ISAs are proprietary. A free and open ISA standard has the potential to increase innovation in microprocessor design, reduce computer system cost, and, as Moore’s law wanes, ease the transition to more specialized computational devices. In this dissertation, I present the RISC-V instruction set architecture. RISC-V is a free and open ISA that, with three decades of hindsight, builds and improves upon the original Reduced Instruction Set Computer (RISC) architectures. It is structured as a small base ISA with a variety of optional extensions. The base ISA is very simple, making RISC-V suitable for research and education, but complete enough to be a suitable ISA for inexpensive, lowpower embedded devices. The optional extensions form a more powerful ISA for generalpurpose and high-performance computing. I also present and evaluate a new RISC-V ISA extension for reduced code size, which makes RISC-V more compact than all popular 64-bit ISAs.


Technical Report

Author: Andrew Waterman
Publication Date: January 2016
Conference: Technical Report No. UCB/EECS-2016-1