RISC-V (pronounced “risk-5”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but which we now hope will become a standard open architecture for industry implementations. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley, but has been made freely available open-source under the BSD license for anyone to use.
In addition, we hope you can join us at the first RISC-V workshop and bootcamp in Monterey CA, January 14-15, 2015.The goals of this workshop are to inform the community of recent activity in the various RISC-V projects underway around the globe and to build consensus on future steps in the RISC-V project, while the bootcamp provides an opportunity to learn about the existing RISC-V infrastructure from the RISC-V development team. The workshop and bootcamp will feature demos of multiple RISC-V silicon tapeouts as well as FPGA board designs and associated software tools.
Registration is FREE for sponsors and affiliates of the ASPIRE laboratory, as well as for UC Berkeley faculty, staff, students, and Non-UCB academics.
General registration is $75 (or $60 Early Bird rate) for the Workshop or the Boot Camp, or $129 (or $99 Early Bird rate) for both.
Early Bird rate expires Dec 1, 2014.