The Agile Process comes to Hardware

David Patterson

EE Times is running a 3-part blog by Bora Nikolić and myself on the benefits of Agile hardware development, which we have been following in building RISC-V chips. (If you want to learn more about software Agile development, I can recommend at inexpensive book:) Engineering Software as a Service: An Agile Approach Using Cloud Computing, by Armando Fox & David Patterson, 2013.

In Part I (which appeared 7/27/15) we defined Agile hardware development as a process of designing a sequence of working but incomplete prototype chips by a small team, rather than One Big Tapeout at the end of a Waterfall process.

In Part II (which appeared 7/30/15) we show that a 28 nm prototype run can cost only $30,000, which calls into question the high cost of designing SoCs using a Waterfall process. We also offer guidelines to lower costs: 1) Have a scalable design so that you can use the lowest-cost die for the prototype run; 2) Reduce the cost of verification and validation by iterating Agile prototypes; 3) Reduce the cost of design and verification by leveraging ideas from modern programming languages that increase reuse; and 4) Reduce software SoC costs by having IP enhance a common, small, free instruction set like RISC-V to reduce the number of software stacks.

Part III (which appeared 8/3/15) is inspired by the guideline 3) above. We show how advances in programming languages that are embraced by Chisel allow us to design a crossbar switch in just 10 lines of code. Our goal with this example is to inspire hardware engineers to upgrade their programming chops so as to become as productive as their software colleagues.

Moore’s Law B. 1965, D. 2015

David Patterson

Gordon Moore (Berkeley class of 1959) made the most incredible technology observation* on April 19, 1965 when he suggested that the number of transistors per integrated circuit would double every year, so that by 1975 there could be 65,000 transistors on a single chip when there were only 64 in 1965. It’s a bold prediction of exponential growth. ( See related article in Barrons ).

Here is his second paragraph on the consequences of such growth:

“Integrated circuits will lead to such wonders as home computers—or at least terminals connected to a central computer—automatic controls for automobiles, and personal portable communications equipment. The electronic wristwatch needs only a display to be feasible today.”

Moore’s Law lasted for half a century and changed the world as Moore predicted in his 1965 article, but it has ended. Chip technology is still improving, but not at the exponential rate predicted by Moore’s Law. In fact, each generation is taking longer than the previous one. For example, the biggest Intel microprocessor in 2011 used 2.3 billion transistors, and 4 years later the largest one is “only” 5.5 billion transistors. It’s still an amazing technology, and it will continue to improve, but not at the breathtaking rate of the past 50 years.

In 2003 Gordon Moore said

“No exponential is forever … but we can delay ‘forever’.”

Looks like forever was delayed another decade, but no more.

*Gordon E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, pp. 114–117, April 19, 1965.

Registration Now Open!! 2nd RISC-V Workshop June 29 – 30, 2015


Registration Now Open!

Please join us for the 2nd RISC-V workshop at The International House , Berkeley June 29-30, 2015. The goals of this workshop are for the community to share information about recent activity in the various RISC-V projects underway around the globe, and to build consensus on future steps in the RISC-V project, including the RISC-V foundation.

We are seeking proposals for talks and posters, with submissions due by 11:59:59PM Pacific Daylight Savings Time, Sunday May 31 and notification by Friday June 5.  Submission website is at

RISC-V (pronounced “risk-5”) is a new instruction set architecture (ISA) that was originally computer architecture research and education, but which we now hope will also become a standard open architecture for industry implementations. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley, but the specification has been made freely available for anyone to use.

Space will be limited, so please register early! Early Bird registration ends June 1st.


-Registration fees will be waived for all UCB and non-UCB academics, as well as employees of sponsors and affiliates of the ASPIRE Laboratory.

-General Registration is $149 through June 1 (early bird special), and $199 thereafter. Registration includes breakfast and lunch both days, and dinner on the first evening.

Coming Soon.

Learn More:

See videos from the 1st RISC-V workshop and bootcamp in January Here




Paper co-authored by ASPIRE student Martin Maas and ASPIRE alum Mohit Tiwari wins ASPLOS 2015 Best Paper Award

Krste Asanovic

The ASPLOS 2015 Best Paper Award was presented to Chang Liu, Austin Harris, Martin Maas, Michael Hicks, Mohit Tiwari, and Elaine Shi for “GhostRider: A Hardware-Software System for Memory Trace Oblivious Computation”.

Martin Maas is a graduate student in the ASPIRE lab, and Mohit Tiwari was a postdoc in the lab before taking his current faculty position at UT Austin.  The paper authors includes members from University of Maryland, University of Texas at Austin, and University of California, Berkeley.

The paper looks at a combined hardware/software approach to providing efficient secure computation and uses the Berkeley-developed Rocket RISC-V infrastructure running on a Convey FPGA system for evaluation.

Congratulations to the whole team!



First RISC-V Workshop Filling up Fast!

Krste Asanovic

We’re down to the last handful of slots to attend the First RISC-V Workshop and Bootcamp on January 14-15, 2015 in Monterey.

Registration is FREE for sponsors and affiliates of the ASPIRE laboratory, as well as for UC Berkeley faculty, staff, students, and Non-UCB academics.

General registration is $75 for the Workshop or the Boot Camp, or $129 for both.

If all seats fill up, we’ll institute a wait list in case of cancellations.