Publications
- An Agile Approach to Building RISC-V Microprocessors
- A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI
- The Hwacha Vector-Fetch Architecture Manual, Version 3.8.1
- Design of the RISC-V Instruction Set Architecture
- The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0
- The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.0
- A Case for OS-Friendly Hardware Accelerators