The Agile Process comes to Hardware

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EE Times is running a 3-part blog by Bora Nikolić and myself on the benefits of Agile hardware development, which we have been following in building RISC-V chips. (If you want to learn more about software Agile development, I can recommend at inexpensive book:) Engineering Software as a Service: An Agile Approach Using Cloud Computing, by Armando Fox & David Patterson, 2013.

In Part I (which appeared 7/27/15) we defined Agile hardware development as a process of designing a sequence of working but incomplete prototype chips by a small team, rather than One Big Tapeout at the end of a Waterfall process.

In Part II (which appeared 7/30/15) we show that a 28 nm prototype run can cost only $30,000, which calls into question the high cost of designing SoCs using a Waterfall process. We also offer guidelines to lower costs: 1) Have a scalable design so that you can use the lowest-cost die for the prototype run; 2) Reduce the cost of verification and validation by iterating Agile prototypes; 3) Reduce the cost of design and verification by leveraging ideas from modern programming languages that increase reuse; and 4) Reduce software SoC costs by having IP enhance a common, small, free instruction set like RISC-V to reduce the number of software stacks.

Part III (which appeared 8/3/15) is inspired by the guideline 3) above. We show how advances in programming languages that are embraced by Chisel allow us to design a crossbar switch in just 10 lines of code. Our goal with this example is to inspire hardware engineers to upgrade their programming chops so as to become as productive as their software colleagues.